1. Field of the Invention
The present invention relates to a phase selector.
2. Description of Related Art
In recent years, along with the development of technologies, the speed of optical communication system has been increased in order to achieve wider digital communication bandwidth. In the specification of optical communication, it is very important for a transmitter to synchronize the data and a clock signal received in parallel, wherein the phases of the data and the clock signal have to be calibrated first.
A delay locked loop (DLL) is usually used in a communication/information system as a clock control circuit, and which synchronizes the output signal with a reference clock signal in the circuit or allows the two to have a fixed phase delay. The DLL is always used as a clock synchronization circuit thanks to the low jitter thereof. FIG. 1 is a block diagram of a conventional phase selector 100. FIG. 2 illustrates the waveforms of a plurality of clock signals received by the phase selector 100 in FIG. 1. Referring to FIG. 1 and FIG. 2, the phase selector 100 includes N buffers B-1-B-N and an N-to-1 multiplexer 102, wherein N is a positive integer. A DLL 10 outputs N clock signals CLK-1-CLK-N according to a reference clock signal CLKref. The DLL 10 provides all the generated phases (i.e., the N clock signals CLK-1-CLK-N having different phases) to the phase selector 100. These phases (the clock signals CLK-1-CLK-N) are respectively transmitted to the multiplexer 102 through the buffers B-1-B-N. The multiplexer 102 selects one of the N phases (the clock signals) according to a selecting signal S. However, the greater the number N of candidate phases (the clock signals CLK-1-CLK-N) is, the more input buffers B-1-B-N have to be disposed in the phase selector 100, and accordingly the greater the size of the multiplexer 102 and the higher the power consumption of the phase selector 100 are.